Low Energy Instruction Memory Organization for Embedded Processors

mbedded systems are electronic systems that have permeated into many aspects of our lives. We can sense the presence of such systems in automobiles, house-hold appliances, consumer electronics and several others. In particular, demand for multimedia applications based embedded systems has been growing at an impressive rate. One of the distinguishing characteristics of such systems is that they are battery operated. For these batteries to long last the systems must be energy efficient. One of the principal component of such systems is a programmable processor, and in many cases it is often a Very Large Instruction Word (VLIW) processor. However, energy analysis of such processors indicate that within these processors, a significant amount of energy is consumed in instruction memories. In this thesis, we address the issue of improving energy efficiency in the instruction memory hierarchy of embedded processors targeted for multimedia applications. The solution to this problem as described in this dissertation, is leveraged upon two key factors. First, from the technological point of view, small and distributed memories can be energy efficient. Second, from the application point of view, significant part of execution time in multimedia applications is dominated by small loops. Motivated by these two key factors, we propose a clustered L0 buffer organization template at the microarchitectural abstraction level. Essentially the clustered organization is distributed loop buffer organization used exclusively for storing and executing instructions of loop kernels. Execution of regular loops, nested loops and loops with conditional constructs are supported in the clustered L0 buffer operation. Furthermore, we expose the L0 clusters to compiler (architecture) and software abstraction levels. At the architectural level, we present an L0 cluster generation tool, which generates an optimal L0 cluster configuration for a given schedule of an application. At the compiler level, we present an algorithm to perform operation scheduling and L0 cluster assignment for a given L0 cluster configuration. Through simulation results we show that instruction memory energy can be reduced by a factor of 6 compared to an organization with no loop buffers and by a factor of 3 compared to a centralized loop buffer organization.